35 search results - page 4 / 7 » Dynamically reconfigurable cache architecture using adaptive... |
SIGARCH
2008
13 years 9 months ago
2008
1 This paper presents a simple but effective method to reduce on-chip access latency and improve core isolation in CMP Non-Uniform Cache Architectures (NUCA). The paper introduces ...
DAC
2009
ACM
14 years 2 months ago
2009
ACM
Dynamic binary translation (DBT) can be used to address important issues in embedded systems. DBT systems store translated code in a software-managed code cache. Unlike general-pu...
ECRTS
2006
IEEE
14 years 4 months ago
2006
IEEE
Cache memories have been extensively used to bridge the gap between high speed processors and relatively slower main memories. However, they are sources of predictability problems...
ISCA
2000
IEEE
14 years 1 months ago
2000
IEEE
High performance general-purpose processors are increasingly being used for a variety of application domains scienti c, engineering, databases, and more recently, media processing...
CODES
2011
IEEE
12 years 9 months ago
2011
IEEE
We propose a novel scheme for run-time management of mixedgrained reconfigurable fabric for the purpose of simultaneous multi-tasking in multi-core reconfigurable processors. Trad...