696 search results - page 6 / 140 » E*plore-ing the Simulation Design Space |
WSC
2007
13 years 9 months ago
2007
We discuss SBatch, a simplified procedure for steady-state simulation analysis that is based on spaced batch means, incorporating many advantages of its predecessorsASAP3 and WAS...
ESTIMEDIA
2007
Springer
14 years 1 months ago
2007
Springer
This paper presents a technique for high-level power estimation of microprocessors. The technique, which is based on abstract execution profiles called ’event signatures’, op...
ISCA
2000
IEEE
13 years 12 months ago
2000
IEEE
As microprocessors continue to evolve, many optimizations reach a point of diminishing returns. We introduce HLS, a hybrid processor simulator which uses statistical models and sy...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
Rapid design space exploration with accurate models is necessary to improve designer productivity at the electronic system level. We describe how to use a new event-based design f...
CODES
2008
IEEE
14 years 1 months ago
2008
IEEE
Application-specific system-on-chip platforms create the opportunity to customize the cache configuration for optimal performance with minimal chip estate. Simulation, in partic...