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ICCAD
2008
IEEE
147views Hardware» more  ICCAD 2008»
14 years 5 months ago
Overlay aware interconnect and timing variation modeling for double patterning technology
— As Double Patterning Technology (DPT) becomes the only solution for 32-nm lithography process, we need to investigate how DPT affects the performance of a chip. In this paper, ...
Jae-Seok Yang, David Z. Pan
HICSS
2009
IEEE
173views Biometrics» more  HICSS 2009»
14 years 3 months ago
Effects of Task Types and Communication Support Tools on E-Negotiation Performance: A Task-Technology Fit Perspective
The rapid growth of the Internet has made computer-mediated communication popular and the use of e-negotiation systems (ENS) has attracted great attention from researchers and pra...
Her-Sen Doong, Hui-Chih Wang, Chi-Kuang Hsieh
DATE
2007
IEEE
150views Hardware» more  DATE 2007»
14 years 3 months ago
A low-SER efficient core processor architecture for future technologies
Device scaling in new and future technologies brings along severe increase in the soft error rate of circuits, for combinational and sequential logic. Although potential solutions...
Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa...
IEEESCC
2007
IEEE
14 years 3 months ago
Brave New Web: Emerging Design Principles and Technologies as Enablers of a Global SOA
Web Services have experienced great interest during the last years as they were expected to play a key role as enablers of seamless application-to-application integration both wit...
Christoph Schroth, Oliver Christ
SBACPAD
2007
IEEE
157views Hardware» more  SBACPAD 2007»
14 years 2 months ago
Exploring Novel Parallelization Technologies for 3-D Imaging Applications
Multi-dimensional imaging techniques involve the processing of high resolution images commonly used in medical, civil and remote-sensing applications. A barrier commonly encounter...
Diego Rivera, Dana Schaa, Micha Moffie, David R. K...