18 search results - page 1 / 4 » EVAL: Utilizing processors with variation-induced timing err... |
MICRO
2008
IEEE
14 years 5 months ago
2008
IEEE
Parameter variation in integrated circuits causes sections of a chip to be slower than others. If, to prevent any resulting timing errors, we design processors for worst-case para...
IEEEPACT
2009
IEEE
13 years 9 months ago
2009
IEEE
Abstract--Chip-MultiProcessor (CMP) architectures are becoming more and more popular as an alternative to the traditional processors that only extract instruction-level parallelism...
CODES
2008
IEEE
14 years 5 months ago
2008
IEEE
To provide Quality of Service (QoS) guarantees in open and unpredictable environments, the utilization control problem is defined to keep the processor utilization at the schedula...
ISCA
2012
IEEE
12 years 1 months ago
2012
IEEE
A significant portion of the energy dissipated in modern integrated circuits is consumed by the overhead associated with timing guardbands that ensure reliable execution. Timing ...
DSN
2007
IEEE
14 years 5 months ago
2007
IEEE
Aggressive CMOS scaling will make future chip multiprocessors (CMPs) increasingly susceptible to transient faults, hard errors, manufacturing defects, and process variations. Exis...