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DATE
2003
IEEE
109views Hardware» more  DATE 2003»
14 years 1 months ago
A Novel Metric for Interconnect Architecture Performance
We propose a new metric for evaluation of interconnect architectures. This metric is computed by optimal assignment of wires from a given wire length distribution (WLD) to a given...
Parthasarathi Dasgupta, Andrew B. Kahng, Swamy Mud...
FCCM
2009
IEEE
134views VLSI» more  FCCM 2009»
14 years 8 days ago
Efficient Mapping of Hardware Tasks on Reconfigurable Computers Using Libraries of Architecture Variants
Scheduling and partitioning of task graphs on reconfigurable hardware needs to be carefully carried out in order to achieve the best possible performance. In this paper, we demons...
Miaoqing Huang, Vikram K. Narayana, Tarek A. El-Gh...
SAT
2005
Springer
162views Hardware» more  SAT 2005»
14 years 1 months ago
Heuristics for Fast Exact Model Counting
An important extension of satisfiability testing is model-counting, a task that corresponds to problems such as probabilistic reasoning and computing the permanent of a Boolean ma...
Tian Sang, Paul Beame, Henry A. Kautz
AFRICACRYPT
2010
Springer
13 years 11 months ago
Practical Improvements of Profiled Side-Channel Attacks on a Hardware Crypto-Accelerator
Abstract. This article investigates the relevance of the theoretical framework on profiled side-channel attacks presented by F.-X. Standaert et al. at Eurocrypt 2009. The analyses ...
M. Abdelaziz Elaabid, Sylvain Guilley
DAC
2004
ACM
14 years 1 months ago
Hierarchical approach to exact symbolic analysis of large analog circuits
—This paper proposes a novel approach to the exact symbolic analysis of very large analog circuits. The new method is based on determinant decision diagrams (DDDs) representing s...
Sheldon X.-D. Tan, Weikun Guo, Zhenyu Qi