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ASPDAC
2005
ACM
100views Hardware» more  ASPDAC 2005»
15 years 7 months ago
Microarchitecture evaluation with floorplanning and interconnect pipelining
— As microprocessor technology continues to scale into the nanometer regime, recent studies show that interconnect delay will be a limiting factor for performance, and multiple c...
Ashok Jagannathan, Hannah Honghua Yang, Kris Konig...
RTCSA
2007
IEEE
15 years 11 months ago
An MPSoC Performance Estimation Framework Using Transaction Level Modeling
— To use the tremendous hardware resources available in next generation MultiProcessor Systems-on-Chip (MPSoC) efficiently, rapid and accurate design space exploration (DSE) met...
Rabie Ben Atitallah, Smaïl Niar, Samy Meftali...
CLEAR
2007
Springer
178views Biometrics» more  CLEAR 2007»
15 years 11 months ago
The CLEAR 2007 Evaluation
This paper is a summary of the 2007 CLEAR Evaluation on the Classification of Events, Activities, and Relationships which took place in early 2007 and culminated with a two-day wo...
Rainer Stiefelhagen, Keni Bernardin, Rachel Bowers...
WER
2007
Springer
15 years 11 months ago
Test-case Driven versus Checklist-based Inspections of Software Requirements - An Experimental Evaluation
Software inspections have proved to be an effective means to find faults in different software artifacts, and the application of software inspections on requirements specification...
Nina Dzamashvili-Fogelström, Tony Gorschek
ICCD
2006
IEEE
118views Hardware» more  ICCD 2006»
16 years 2 months ago
A System-level Network-on-Chip Simulation Framework Integrated with Low-level Analytical Models
—This paper presents a system-level Network-on-Chip modeling framework that integrates transaction-level model and analytical wire model for design space exploration. It enables ...
Jinwen Xi, Peixin Zhong