— As microprocessor technology continues to scale into the nanometer regime, recent studies show that interconnect delay will be a limiting factor for performance, and multiple c...
— To use the tremendous hardware resources available in next generation MultiProcessor Systems-on-Chip (MPSoC) efficiently, rapid and accurate design space exploration (DSE) met...
This paper is a summary of the 2007 CLEAR Evaluation on the Classification of Events, Activities, and Relationships which took place in early 2007 and culminated with a two-day wo...
Software inspections have proved to be an effective means to find faults in different software artifacts, and the application of software inspections on requirements specification...
—This paper presents a system-level Network-on-Chip modeling framework that integrates transaction-level model and analytical wire model for design space exploration. It enables ...