45 search results - page 6 / 9 » Effect of Channel-Quality Indicator Delay on HSDPA Performan... |
FPL
2005
Springer
14 years 1 months ago
2005
Springer
This work explores the effect of adding a timing driven functional decomposition step to the traditional field programmable gate array (FPGA) CAD flow. Once placement has comple...
ICC
2009
IEEE
14 years 2 months ago
2009
IEEE
—This study presents a cross-layer fast handover scheme for VANET, called vehicular fast handover scheme (VFHS), where the physical layer information is shared with the MAC layer...
FPGA
2003
ACM
14 years 25 days ago
2003
ACM
We present a pipelining-aware router for FPGAs. The problem of routing pipelined signals is different from the conventional FPGA routing problem. For example, the two terminal N-D...
HRI
2007
ACM
13 years 11 months ago
2007
ACM
When a robot provides direction--as a guide, an assistant, or as an instructor--the robot may have to interact with people of different backgrounds and skill sets. Different peopl...
ISPASS
2006
IEEE
14 years 1 months ago
2006
IEEE
— Due to the long simulation times of the reference input sets, microarchitects resort to alternative techniques to speed up cycle-accurate simulations. However, the reduction in...