137 search results - page 17 / 28 » Effect of Event Orderings on Memory Requirement in Parallel ... |
CF
2009
ACM
14 years 1 months ago
2009
ACM
Chip Multiprocessor (CMP) memory systems suffer from the effects of destructive thread interference. This interference reduces performance predictability because it depends heavil...
ARCS
2009
Springer
14 years 1 months ago
2009
Springer
The disparity between microprocessor clock frequencies and memory latency is a primary reason why many demanding applications run well below peak achievable performance. Software c...
ISCA
2010
IEEE
13 years 10 months ago
2010
IEEE
GPU architectures are increasingly important in the multi-core era due to their high number of parallel processors. Performance optimization for multi-core processors has been a c...
ISCA
2010
IEEE
13 years 11 months ago
2010
IEEE
Given the multicore microprocessor revolution, we argue that the architecture research community needs a dramatic increase in simulation capacity. We believe FPGA Architecture Mod...
IPPS
2010
IEEE
13 years 4 months ago
2010
IEEE
Abstract--Uintah is a highly parallel and adaptive multiphysics framework created by the Center for Simulation of Accidental Fires and Explosions in Utah. Uintah, which is built up...