137 search results - page 4 / 28 » Effect of Event Orderings on Memory Requirement in Parallel ... |
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
The performance of computer systems depends, among other things, on the workload. This motivates the use of real workloads (as recorded in activity logs) to drive simulations of n...
CPHYSICS
2010
13 years 7 months ago
2010
In this paper, a programming model is presented which enables scalable parallel performance on multi-core shared memory architectures. The model has been developed for application...
CASES
2003
ACM
14 years 19 days ago
2003
ACM
—We investigate the problem of memory reuse in order to reduce the memory needed to store an array variable. We develop techniques that can lead to smaller memory requirements in...
IPPS
2000
IEEE
13 years 11 months ago
2000
IEEE
We consider networks of workstations which are not only timesharing, but also heterogeneous with a large variation in the computing power and memory capacities of different workst...
EUROPAR
2008
Springer
13 years 9 months ago
2008
Springer
Chip multiprocessors designed for streaming applications such as Cell BE offer impressive peak performance but suffer from limited bandwidth to offchip main memory. As the number o...