Sciweavers

832 search results - page 31 / 167
» Effect of Malicious Synchronization
Sort
View
DATE
1999
IEEE
127views Hardware» more  DATE 1999»
14 years 2 months ago
Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits
This paper investigates retiming and clock skew scheduling for improving the tolerance of synchronous circuits to delay variations. It is shown that when both long and short paths...
Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman
ICCAD
1997
IEEE
147views Hardware» more  ICCAD 1997»
14 years 2 months ago
Built-in test generation for synchronous sequential circuits
We consider the problem of built-in test generation for synchronous sequential circuits. The proposed scheme leaves the circuit flip-flops unmodified, and thus allows at-speed ...
Irith Pomeranz, Sudhakar M. Reddy
HPDC
2000
IEEE
14 years 2 months ago
Synchronizing Network Probes to Avoid Measurement Intrusiveness with the Network Weather Service
In this paper we present a scalable protocol for conducting periodic probes of network performance in a way that minimizes collisions between separate probes. The goal of the prot...
Richard Wolski, Benjamin Gaidioz, Bernard Touranch...
MTA
2002
136views more  MTA 2002»
13 years 9 months ago
Dealing with Uncertain Durations in Synchronized Multimedia Presentations
In this paper, we discuss the effect of the uncertainty in the duration of some multimedia objects on the quality of the presentation of multimedia scenarios. This uncertainty can ...
Nabil Layaïda, Loay Sabry-Ismaïl, C&eacu...
EMNLP
2009
13 years 7 months ago
Feature-Rich Translation by Quasi-Synchronous Lattice Parsing
We present a machine translation framework that can incorporate arbitrary features of both input and output sentences. The core of the approach is a novel decoder based on lattice...
Kevin Gimpel, Noah A. Smith