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» Effective Program Verification for Relaxed Memory Models
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IISWC
2008
IEEE
14 years 1 months ago
Accelerating multi-core processor design space evaluation using automatic multi-threaded workload synthesis
The design and evaluation of microprocessor architectures is a difficult and time-consuming task. Although small, handcoded microbenchmarks can be used to accelerate performance e...
Clay Hughes, Tao Li
CI
2000
114views more  CI 2000»
13 years 7 months ago
A Guided Tour through Some Extensions of the Event Calculus
Kowalski and Sergot's Event Calculus (EC) is a simple temporal formalism that, given a set of event occurrences, derives the maximal validity intervals (MVIs) over which prop...
Iliano Cervesato, Massimo Franceschet, Angelo Mont...
JPDC
2006
106views more  JPDC 2006»
13 years 7 months ago
Performance characteristics of the multi-zone NAS parallel benchmarks
We describe a new suite of computational benchmarks that models applications featuring multiple levels of parallelism. Such parallelism is often available in realistic flow comput...
Haoqiang Jin, Rob F. Van der Wijngaart
TSE
2010
180views more  TSE 2010»
13 years 5 months ago
Aspect-Oriented Race Detection in Java
—In the past, researchers have developed specialized programs to aid programmers in detecting concurrent programming errors such as deadlocks, livelocks, starvation, and data rac...
Eric Bodden, Klaus Havelund
MICRO
2003
IEEE
125views Hardware» more  MICRO 2003»
14 years 11 days ago
WaveScalar
Silicon technology will continue to provide an exponential increase in the availability of raw transistors. Effectively translating this resource into application performance, how...
Steven Swanson, Ken Michelson, Andrew Schwerin, Ma...