64 search results - page 5 / 13 » Effects of on-chip inductance on power distribution grid |
DAC
1999
ACM
14 years 8 months ago
1999
ACM
- A closed form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range o...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
Power distribution and signal transmission are becoming key limiters for chip performance in nanometer era. These issues can be simultaneously addressed by designing transmission ...
CCGRID
2004
IEEE
13 years 11 months ago
2004
IEEE
Grid computing promises the ability to share geographically and organizationally distributed resources to increase effective computational power and resource utilization. However,...
TVLSI
2002
13 years 7 months ago
2002
Simultaneous switching noise (SSN) has become an important issue in the design of the internal on-chip power distribution networks in current very large scale integration/ultra lar...
DAC
2012
ACM
11 years 10 months ago
2012
ACM
Due to the large geometry of through-silicon-vias (TSVs) and their connections to the power grid, significant current crowding can occur in 3D ICs. Prior works model TSVs and pow...