778 search results - page 79 / 156 » Efficient Code Generation for Automatic Parallelization and ... |
ICCAD
2001
IEEE
14 years 6 months ago
2001
IEEE
Efficient high level design tools that can map behavioral descriptions to FPGA architectures are one of the key requirements to fully leverage FPGA for high throughput computatio...
EUROPAR
2009
Springer
14 years 3 months ago
2009
Springer
It is an important problem to map virtual parallel processes to physical processors (or cores) in an optimized way to get scalable performance due to non-uniform communication cost...
ICPP
2009
IEEE
13 years 7 months ago
2009
IEEE
Peer-to-peer (P2P) storage systems rely on data redundancy to obtain high levels of data availability. Among the existing data redundancy schemes, erasure coding is a widely adopte...
CGO
2008
IEEE
14 years 3 months ago
2008
IEEE
The recent trend in the processor industry of packing multiple processor cores in a chip has increased the importance of automatic techniques for extracting thread level paralleli...
CODES
2005
IEEE
14 years 2 months ago
2005
IEEE
This paper presents a novel approach for multiprocess synthesis supporting well-tailored module integration at system level. The goal is to extend the local scope of existing arch...