To keep up with a large degree of instruction level parallelism (ILP), the Itanium 2 cache systems use a complex organization scheme: load/store queues, banking and interleaving. ...
William Jalby, Christophe Lemuet, Sid Ahmed Ali To...
Abstract--Energy-efficient optical networks are gaining momentum as environmental-friendly solutions with reduced operational costs. Energy-efficiency can be achieved by using devi...
Ajmal Muhammad, Paolo Monti, Isabella Cerutti, Len...
— Prior work has shown that network capacity efficiency decreases significantly as a network’s topology becomes sparse. Meta-mesh restoration was proposed in prior work as a me...
This paper proposes an efficient method to find the worst case of voltage violation by multi-domain clock gating in an on-chip power network. We first present a voltage response i...
Wanping Zhang, Yi Zhu, Wenjian Yu, Ling Zhang, Rui...
When modern processors keep increasing the instruction window size and the issue width to exploit more instruction-level parallelism (ILP), the demand of larger physical register ...