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» Efficient Design Error Correction of Digital Circuits
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DAC
1994
ACM
14 years 24 days ago
Statistical Estimation of the Switching Activity in Digital Circuits
Higher levels of integration have led to a generation of integrated circuits for which power dissipation and reliability are major design concerns. In CMOS circuits, both of these ...
Michael G. Xakellis, Farid N. Najm
SIGCOMM
2010
ACM
13 years 9 months ago
Efficient error estimating coding: feasibility and applications
Motivated by recent emerging systems that can leverage partially correct packets in wireless networks, this paper investigates the novel concept of error estimating codes (EEC). W...
Binbin Chen, Ziling Zhou, Yuda Zhao, Haifeng Yu
GLVLSI
2006
IEEE
105views VLSI» more  GLVLSI 2006»
14 years 2 months ago
A practical approach for monitoring analog circuits
Formal methods have been advocated for the verification of digital design where correctness is proved mathematically. In contrast to digital designs, the verification of analog ...
Mohamed H. Zaki, Sofiène Tahar, Guy Bois
DAC
2005
ACM
13 years 10 months ago
Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits
Reliability of nanometer circuits is becoming a major concern in today’s VLSI chip design due to interferences from multiple noise sources as well as radiation-induced soft erro...
Chong Zhao, Yi Zhao, Sujit Dey
ICCD
2002
IEEE
110views Hardware» more  ICCD 2002»
14 years 5 months ago
Efficient PEEC-Based Inductance Extraction Using Circuit-Aware Techniques
Practical approaches for on-chip inductance extraction to obtain a sparse, stable and accurate inverse inductance matrix K are proposed. The novelty of our work is in using circui...
Haitian Hu, Sachin S. Sapatnekar