303 search results - page 16 / 61 » Efficient Design Error Correction of Digital Circuits |
ISCAS
2007
IEEE
14 years 3 months ago
2007
IEEE
—Two probabilistic-based models, namely the Ensemble-Dependent Matrix model [1][3] and the Markov Random Field model [2], have been proposed to deal with faults in nanoscale syst...
TCAD
2002
13 years 8 months ago
2002
Abstract--This paper investigates the application of simultaneous retiming and clock scheduling for optimizing synchronous circuits under setup and hold constraints. Two optimizati...
DAC
2008
ACM
14 years 9 months ago
2008
ACM
In this paper, we present ELIAD, an efficient lithography aware detailed router to optimize silicon image after optical proximity correction (OPC) in a correct-by-construction man...
IEICET
2008
13 years 8 months ago
2008
We developed a content delivery system using a partially reconfigurable FPGA to securely distribute digital content on the Internet. With partial reconfigurability of a Xilinx Vir...
CHINAF
2006
13 years 8 months ago
2006
: With soaring work frequency and decreasing feature sizes, VLSI circuits with RLC parasitic components are more like analog circuits and should be carefully analyzed in physical d...