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» Efficient Design Error Correction of Digital Circuits
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DATE
2007
IEEE
119views Hardware» more  DATE 2007»
14 years 3 months ago
Experimental evaluation of protections against laser-induced faults and consequences on fault modeling
Lasers can be used by hackers to situations to inject faults in circuits and induce security flaws. On-line detection mechanisms are classically proposed to counter such attacks, ...
Régis Leveugle, Abdelaziz Ammari, V. Maingo...
DAC
2005
ACM
14 years 9 months ago
Simulation models for side-channel information leaks
Small, embedded integrated circuits (ICs) such as smart cards are vulnerable to so-called side-channel attacks (SCAs). The attacker can gain information by monitoring the power co...
Kris Tiri, Ingrid Verbauwhede
CASES
2010
ACM
13 years 6 months ago
Implementing virtual secure circuit using a custom-instruction approach
Although cryptographic algorithms are designed to resist at least thousands of years of cryptoanalysis, implementing them with either software or hardware usually leaks additional...
Zhimin Chen, Ambuj Sinha, Patrick Schaumont
FDL
2003
IEEE
14 years 2 months ago
Using Symbolic Simulation for Bounded Property Checking
Assuring correctness of digital designs is one of the major tasks in the system design flow. Formal methods have been proposed to accompany commonly used simulation approaches. I...
Jürgen Ruf, Prakash Mohan Peranandam, Thomas ...
FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
14 years 5 months ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson