303 search results - page 39 / 61 » Efficient Design Error Correction of Digital Circuits |
DAC
2008
ACM
14 years 9 months ago
2008
ACM
As integrated circuit technology plumbs ever greater depths in the scaling of feature sizes, maintaining the paradigm of deterministic Boolean computation is increasingly challeng...
PADS
2003
ACM
14 years 2 months ago
2003
ACM
There is a wide-spread usage of hardware design languages(HDL) to speed up the time-to-market for the design of modern digital systems. Verification engineers can simulate hardwa...
DATE
2009
IEEE
14 years 19 days ago
2009
IEEE
In the digital VLSI cycle, logic transformations are often required to modify the design to meet different synthesis and optimization goals. Logic transformations on sequential ci...
SIGSOFT
2003
ACM
14 years 9 months ago
2003
ACM
Memory corruption errors lead to non-deterministic, elusive crashes. This paper describes ARCHER (ARray CHeckER) a static, effective memory access checker. ARCHER uses path-sensit...
BMCBI
2006
13 years 8 months ago
2006
Background: In binary high-throughput screening projects where the goal is the identification of low-frequency events, beyond the obvious issue of efficiency, false positives and ...