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» Efficient Design Error Correction of Digital Circuits
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DAC
2007
ACM
14 years 9 months ago
Modeling and Estimation of Full-Chip Leakage Current Considering Within-Die Correlation
We present an efficient technique for finding the mean and variance of the full-chip leakage of a candidate design, while considering logic-structures and both die-to-die and with...
Khaled R. Heloue, Navid Azizi, Farid N. Najm
DAC
2005
ACM
14 years 9 months ago
Advanced Timing Analysis Based on Post-OPC Extraction of Critical Dimensions
While performance specifications are verified before sign-off for a modern nanometer scale design, extensive application of optical proximity correction substantially alters the l...
Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Denni...
DAC
2008
ACM
14 years 9 months ago
Parameterized timing analysis with general delay models and arbitrary variation sources
Many recent techniques for timing analysis under variability, in which delay is an explicit function of underlying parameters, may be described as parameterized timing analysis. T...
Khaled R. Heloue, Farid N. Najm
PIMRC
2008
IEEE
14 years 3 months ago
BER analysis of single-carrier MPAM in the presence of ADC quantization noise
— Noisy radio frequency (RF) circuits tend to degrade the system performance, especially in high frequency communication systems. The performance analysis of such systems is norm...
Umar H. Rizvi, Gerard J. M. Janssen, Jos H. Weber
ANCS
2008
ACM
13 years 10 months ago
On design of bandwidth scheduling algorithms for multiple data transfers in dedicated networks
The significance of high-performance dedicated networks has been well recognized due to the rapidly increasing number of large-scale applications that require high-speed data tran...
Yunyue Lin, Qishi Wu