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» Efficient Design Error Correction of Digital Circuits
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IOLTS
2008
IEEE
102views Hardware» more  IOLTS 2008»
14 years 3 months ago
Integrating Scan Design and Soft Error Correction in Low-Power Applications
— Error correcting coding is the dominant technique to achieve acceptable soft-error rates in memory arrays. In many modern circuits, the number of memory elements in the random ...
Michael E. Imhof, Hans-Joachim Wunderlich, Christi...
IPPS
2007
IEEE
14 years 3 months ago
Fast SEU Detection and Correction in LUT Configuration Bits of SRAM-based FPGAs
1 FPGAs are an appealing solution for the space-based remote sensing applications. However, in a low-earth orbit, configuration bits of SRAM-based FPGAs are susceptible to single-e...
Hamid R. Zarandi, Seyed Ghassem Miremadi, Costas A...
ISCAS
2006
IEEE
90views Hardware» more  ISCAS 2006»
14 years 2 months ago
Phase measurement and adjustment of digital signals using random sampling technique
—This paper introduces a technique to measure and adjust the relative phase of on-chip high speed digital signals using a random sampling technique of inferential statistics. The...
Rashed Zafar Bhatti, Monty Denneau, Jeff Draper
EH
2000
IEEE
91views Hardware» more  EH 2000»
14 years 1 months ago
Towards the Automatic Design of More Efficient Digital Circuits
Vesselin K. Vassilev, Dominic Job, Julian F. Mille...
DATE
2009
IEEE
202views Hardware» more  DATE 2009»
14 years 3 months ago
Design as you see FIT: System-level soft error analysis of sequential circuits
Soft errors in combinational and sequential elements of digital circuits are an increasing concern as a result of technology scaling. Several techniques for gate and latch hardeni...
Daniel Holcomb, Wenchao Li, Sanjit A. Seshia