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FPL
2006
Springer
242views Hardware» more  FPL 2006»
13 years 11 months ago
TMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAs
With current FPGAs, designers can now instantiate several embedded processors, memory units, and a wide variety of IP blocks to build a single-chip, high-performance multiprocesso...
Manuel Saldaña, Paul Chow
FPGA
2008
ACM
136views FPGA» more  FPGA 2008»
13 years 9 months ago
A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs
Functional full-system simulators are powerful and versatile research tools for accelerating architectural exploration and advanced software development. Their main shortcoming is...
Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Bab...
EH
2003
IEEE
135views Hardware» more  EH 2003»
14 years 1 months ago
Towards Evolvable IP Cores for FPGAs
The paper deals with a new approach to the design of adaptive hardware using common Field Programmable Gate Arrays (FPGA). The ultimate aim is to develop evolvable IP (Intellectua...
Lukás Sekanina
FPGA
2003
ACM
117views FPGA» more  FPGA 2003»
14 years 28 days ago
Reducing pin and area overhead in fault-tolerant FPGA-based designs
This paper proposes a new high-level technique for designing fault tolerant systems in SRAM-based FPGAs, without modifications in the FPGA architecture. Traditionally, TMR has bee...
Fernanda Lima, Luigi Carro, Ricardo Augusto da Luz...
DATE
2008
IEEE
105views Hardware» more  DATE 2008»
14 years 2 months ago
Comparison of Boolean Satisfiability Encodings on FPGA Detailed Routing Problems
We compare 12 new encodings for representing of FPGA detailed routing problems as equivalent Boolean Satisfiability (SAT) problems against the only 2 previously used encodings. We...
Miroslav N. Velev, Ping Gao 0002