Sciweavers

283 search results - page 23 / 57
» Efficient FPGA hardware development: A multi-language approa...
Sort
View
GLVLSI
2003
IEEE
130views VLSI» more  GLVLSI 2003»
14 years 1 months ago
Zero overhead watermarking technique for FPGA designs
FPGAs, because of their re-programmability, are becoming very popular for creating and exchanging VLSI intellectual properties (IPs) in the reuse-based design paradigm. Existing w...
Adarsh K. Jain, Lin Yuan, Pushkin R. Pari, Gang Qu
FPL
2008
Springer
178views Hardware» more  FPL 2008»
13 years 9 months ago
High-speed regular expression matching engine using multi-character NFA
An approach is presented for high throughput matching of regular expressions (regexes) by first converting them into corresponding Non-deterministic Finite Automata (NFAs) which a...
Norio Yamagaki, Reetinder P. S. Sidhu, Satoshi Kam...
EUROMICRO
1998
IEEE
13 years 12 months ago
Process Scheduling for Performance Estimation and Synthesis of Hardware/Software Systems
The paper presents an approach to process scheduling for embedded systems. Target architectures consist of several processors and ASICs connected by shared busses. We have develop...
Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa...
ERSA
2010
172views Hardware» more  ERSA 2010»
13 years 5 months ago
A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics
Interconnect architecture is a primary research issue for emerging many-core processors. Packet switched Networks-on-Chip (NoCs) are considered key to success but since they delive...
Heiner Giefers, Marco Platzner
FPGA
1995
ACM
118views FPGA» more  FPGA 1995»
13 years 11 months ago
An SBus Monitor Board
During the development of computer peripherals which interface to the processor via the system bus it is often necessary to acquire the signals on the bus at the hardware level. I...
H. A. Xie, Kevin E. Forward, K. M. Adams, D. Leask