283 search results - page 27 / 57 » Efficient FPGA hardware development: A multi-language approa... |
PARELEC
2000
IEEE
14 years 2 days ago
2000
IEEE
The purpose of this paper is to demonstrate the implementation of an adaptable parallel architecture capable of system to task adaptation. The system implementation was based on X...
ISCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
—We present an efficient approach for on-chip frequency response measurement, including phase and gain, of analog circuitry in mixed-signal systems. The approach uses direct digi...
FPL
2000
Springer
13 years 11 months ago
2000
Springer
This paper describes a novel resource binding technique for use in multiple-wordlength systems implemented in FPGAs. It is demonstrated that the multiple-wordlength binding problem...
EMSOFT
2006
Springer
13 years 11 months ago
2006
Springer
Upper bounds on worst-case execution times, which are commonly called WCET, are a prerequisite for validating the temporal correctness of tasks in a real-time system. Due to the e...
FCCM
2004
IEEE
13 years 11 months ago
2004
IEEE
Reconfigurable System-on-Chip (SoC) platforms that incorporate hard-core processors surrounded by large amounts of FPGA are today commodities: the reconfigurable logic is often us...