286 search results - page 22 / 58 » Efficient Hardware Architectures for Modular Multiplication ... |
PDP
2010
IEEE
13 years 12 months ago
2010
IEEE
In the last years high performance processor designs have evolved toward Chip-Multiprocessor (CMP) architectures that implement multiple processing cores on a single die. As the nu...
ASAP
2008
IEEE
14 years 2 months ago
2008
IEEE
Process technology has reduced in size such that it is possible to implement complete applicationspecific architectures as Systems-on-Chip (SoCs) using both Application-Specific I...
MSS
2003
IEEE
14 years 25 days ago
2003
IEEE
In this paper, we present a parallel transmission architecture for SAN. By using two schedulers on the destination and source addresses of packets, the load of multiple data flows...
FPL
2005
Springer
14 years 1 months ago
2005
Springer
Domain-specific heterogeneous reconfigurable arrays provide high performance over generic Field Programmable Gate Arrays (FPGAs) while maintaining the flexibility for that particu...
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
— Significant headway has been made in logic density and performance of FPGAs in the past decade. Power efficiency of FPGA architectures is arguably the next most important crite...