Sciweavers

286 search results - page 24 / 58
» Efficient Hardware Architectures for Modular Multiplication ...
Sort
View
FPL
2006
Springer
108views Hardware» more  FPL 2006»
13 years 11 months ago
Implementation of Network Application Layer Parser for Multiple TCP/IP Flows in Reconfigurable Devices
This paper presents an implementation of a high-performance network application layer parser in FPGAs. At the core of the architecture resides a pattern matcher and a parser. The ...
James Moscola, Young H. Cho, John W. Lockwood
CODES
2005
IEEE
14 years 1 months ago
Future processors: flexible and modular
The ability to continue increasing processor frequency and single thread performance is being severely limited by exponential increases in leakage and active power. To continue to...
Charlie Johnson, Jeff Welser
DATE
1999
IEEE
194views Hardware» more  DATE 1999»
13 years 12 months ago
CRUSADE: Hardware/Software Co-Synthesis of Dynamically Reconfigurable Heterogeneous Real-Time Distributed Embedded Systems
Dynamically reconfigurable embedded systems offer potential for higher performance as well as adaptability to changing system requirements at low cost. Such systems employ run-tim...
Bharat P. Dav
CCS
2007
ACM
13 years 11 months ago
Reconfigurable trusted computing in hardware
Trusted Computing (TC) is an emerging technology towards building trustworthy computing platforms. The Trusted Computing Group (TCG) has proposed several specifications to impleme...
Thomas Eisenbarth, Tim Güneysu, Christof Paar...
FPL
2006
Springer
147views Hardware» more  FPL 2006»
13 years 11 months ago
Efficient Automated Synthesis, Programing, and Implementation of Multi-Processor Platforms on FPGA Chips
Emerging embedded System-on-Chip (SoC) platforms are increasingly becoming multiprocessor architectures. The advances in the FPGA chip technology make the implementation of such a...
Hristo Nikolov, Todor Stefanov, Ed F. Deprettere