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FCCM
2006
IEEE
144views VLSI» more  FCCM 2006»
14 years 1 months ago
Combining Instruction Coding and Scheduling to Optimize Energy in System-on-FPGA
In this paper, we investigate a combination of two techniques — instruction coding and instruction re-ordering — for optimizing energy in embedded processor control. We presen...
Robert G. Dimond, Oskar Mencer, Wayne Luk
FPT
2005
IEEE
117views Hardware» more  FPT 2005»
14 years 1 months ago
FPGA Defect Tolerance: Impact of Granularity
As device sizes shrink, FPGAs are increasingly prone to manufacturing defects. The ability to tolerate multiple defects is anticipated to be very important at 45nm and beyond. One...
Anthony J. Yu, Guy G. Lemieux
FCCM
2005
IEEE
131views VLSI» more  FCCM 2005»
14 years 1 months ago
Automating the Layout of Reconfigurable Subsystems Using Circuit Generators
When designing systems-on-a-chip (SoCs), a unique opportunity exists to generate custom FPGA architectures that are specific to the application domain in which the device will be ...
Shawn Phillips, Scott Hauck
FCCM
2006
IEEE
133views VLSI» more  FCCM 2006»
14 years 1 months ago
A Scalable FPGA-based Multiprocessor
It has been shown that a small number of FPGAs can significantly accelerate certain computing tasks by up to two or three orders of magnitude. However, particularly intensive lar...
Arun Patel, Christopher A. Madill, Manuel Salda&nt...
FPL
2000
Springer
128views Hardware» more  FPL 2000»
13 years 11 months ago
Verification of Dynamically Reconfigurable Logic
This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standa...
David Robinson, Patrick Lysaght