286 search results - page 40 / 58 » Efficient Hardware Architectures for Modular Multiplication ... |
ASPLOS
2010
ACM
13 years 11 months ago
2010
ACM
This paper proposes an efficient hardware/software system that significantly enhances software security through diversified replication on multi-cores. Recent studies show that a ...
ICCD
2006
IEEE
14 years 4 months ago
2006
IEEE
—Network-on-Chip (NoC) has been proposed as an attractive alternative to traditional dedicated wires to achieve high performance and modularity. Power efficiency is one of the mo...
FCCM
2005
IEEE
14 years 1 months ago
2005
IEEE
Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor architectures. We previously in...
IPPS
1996
IEEE
13 years 11 months ago
1996
IEEE
A new VLSI architecture for real-time pipeline FFT processor is proposed. A hardware oriented radix-22 algorithm is derived by integrating a twiddle factor decomposition technique ...
CPHYSICS
2010
13 years 7 months ago
2010
In this paper, a programming model is presented which enables scalable parallel performance on multi-core shared memory architectures. The model has been developed for application...