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ASPDAC
2007
ACM
131views Hardware» more  ASPDAC 2007»
15 years 8 months ago
Fast Flip-Chip Pin-Out Designation Respin by Pin-Block Design and Floorplanning for Package-Board Codesign
Deep submicron effects drive the complication in designing chips, as well as in package designs and communications between package and board. As a result, the iterative interface d...
Ren-Jie Lee, Ming-Fang Lai, Hung-Ming Chen
EUROPAR
2009
Springer
15 years 8 months ago
StarPU: A Unified Platform for Task Scheduling on Heterogeneous Multicore Architectures
Abstract. In the field of HPC, the current hardware trend is to design multiprocessor architectures that feature heterogeneous technologies such as specialized coprocessors (e.g., ...
Cédric Augonnet, Samuel Thibault, Raymond N...
ICCAD
2000
IEEE
153views Hardware» more  ICCAD 2000»
15 years 8 months ago
Slope Propagation in Static Timing Analysis
ct Static timing analysis has traditionally used the PERT method for identifying the critical path of a digital circuit. Due to the influence of the slope of a signal at a particul...
David Blaauw, Vladimir Zolotov, Savithri Sundaresw...
VLDB
1987
ACM
92views Database» more  VLDB 1987»
15 years 7 months ago
Mind Your Grammar: a New Approach to Modelling Text
Beginning to create the New Oxford English Dictionary database has resulted in the realization that databases for reference texts are unlike those for conventional enterprises. Wh...
Gaston H. Gonnet, Frank Wm. Tompa
ANCS
2008
ACM
15 years 6 months ago
Low power architecture for high speed packet classification
Today's routers need to perform packet classification at wire speed in order to provide critical services such as traffic billing, priority routing and blocking unwanted Inte...
Alan Kennedy, Xiaojun Wang, Zhen Liu, Bin Liu