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DELTA
2004
IEEE
15 years 7 months ago
Scan Test of IP Cores in an ATE Environment
Manufacturing test of chips made of multiple IP cores requires different techniques if ATE is used. As scan chains are commonly used as access paths to the DUT, ATE architectures ...
Luca Schiano, Yong-Bin Kim, Fabrizio Lombardi
FCCM
2004
IEEE
87views VLSI» more  FCCM 2004»
15 years 7 months ago
A Quantitative Comparison of Reconfigurable, Tiled, and Conventional Architectures on Bit-Level Computation
General purpose computing architectures are being called on to work on a more diverse application mix every day. This has been fueled by the need for reduced time to market and ec...
David Wentzlaff, Anant Agarwal
CHES
2006
Springer
205views Cryptology» more  CHES 2006»
15 years 7 months ago
Automated Design of Cryptographic Devices Resistant to Multiple Side-Channel Attacks
Balanced dynamic dual-rail gates and asynchronous circuits have been shown, if implemented correctly, to have natural and efficient resistance to side-channel attacks. Despite thei...
Konrad J. Kulikowski, Alexander B. Smirnov, Alexan...
DAC
2006
ACM
15 years 7 months ago
Refined statistical static timing analysis through
Statistical static timing analysis (SSTA) has been a popular research topic in recent years. A fundamental issue with applying SSTA in practice today is the lack of reliable and e...
Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir
DRM
2006
Springer
15 years 7 months ago
Towards a secure and interoperable DRM architecture
In this paper we look at the problem of interoperability of digital rights management (DRM) systems in home networks. We introduce an intermediate module called the Domain Interop...
Gelareh Taban, Alvaro A. Cárdenas, Virgil D...