40 search results - page 6 / 8 » Efficient Mapping of Hardware Tasks on Reconfigurable Comput... |
IPPS
2003
IEEE
14 years 1 months ago
2003
IEEE
This paper presents a technique, called loop dissevering, to temporally partitioning any type of loop presented in programming languages. The technique can be used in the presence...
DATE
2003
IEEE
14 years 1 months ago
2003
IEEE
MorphoSys is a reconfigurable SIMD architecture. In this paper, a BSP-based ray tracing is gracefully mapped onto MorphoSys. The mapping highly exploits ray-tracing parallelism. A...
CORR
2010
Springer
13 years 8 months ago
2010
Springer
The algorithms in the current sequential numerical linear algebra libraries (e.g. LAPACK) do not parallelize well on multicore architectures. A new family of algorithms, the tile a...
DSD
2010
IEEE
13 years 8 months ago
2010
IEEE
— Real-time face recognition by computer systems is required in many commercial and security applications because it is the only way to protect privacy and security in the sea of...
ISCA
2002
IEEE
13 years 7 months ago
2002
IEEE
In this paper, we consider the tree task graphs which arise from many important programming paradigms such as divide and conquer, branch and bound etc., and the linear task-graphs...