279 search results - page 17 / 56 » Efficient Power Co-Estimation Techniques for System-on-Chip ... |
IPCCC
2006
IEEE
14 years 1 months ago
2006
IEEE
Low power has been considered as an important issue in instruction cache (I-cache) designs. Several studies have shown that the I-cache can be tuned to reduce power. These techniq...
DAC
1996
ACM
13 years 11 months ago
1996
ACM
A novel methodology for circuit design and automatic layout generation is proposed for a class of mixed-signal circuits in presence of layout parasitics and substrate induced nois...
SAC
2005
ACM
14 years 29 days ago
2005
ACM
This paper presents an efficient technique for placement and routing of sensors/actuators and processing units in a grid network. Our system requires an extremely high level of ro...
TWC
2008
13 years 7 months ago
2008
Abstract-- In many portable devices, wireless network interfaces consume upwards of 30% of scarce system energy. Reducing the transceiver's power consumption to extend the sys...
ISCAS
2007
IEEE
14 years 1 months ago
2007
IEEE
— This paper describes the hardware architecture for a flexible probability density estimation unit to be used in a Large Vocabulary Speech Recognition System, and targeted for m...