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TCAD
2008
172views more  TCAD 2008»
13 years 7 months ago
General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the mos...
Foad Dabiri, Ani Nahapetian, Tammara Massey, Miodr...
ISQED
2009
IEEE
86views Hardware» more  ISQED 2009»
14 years 2 months ago
Uncriticality-directed scheduling for tackling variation and power challenges
The advance in semiconductor technologies presents the serious problem of parameter variations. They affect threshold voltage of transistors and thus circuit delay has variability...
Toshinori Sato, Shingo Watanabe
DAC
2004
ACM
14 years 8 months ago
FPGA power reduction using configurable dual-Vdd
Power optimization is of growing importance for FPGAs in nanometer technologies. Considering dual-Vdd technique, we show that configurable power supply is required to obtain a sat...
Fei Li, Yan Lin, Lei He
APCCAS
2006
IEEE
272views Hardware» more  APCCAS 2006»
14 years 1 months ago
Power Analysis for the MOS AC/DC Rectifier of Passive RFID Transponders
—The operating principle of MOS FETs AC/DC rectifier for passive RFID transponder is introduced and the power dissipation of MOS rectifier operating with 902M-928MHz industrial, ...
Changming Ma, Chun Zhang, Zhihua Wang
GLVLSI
2003
IEEE
146views VLSI» more  GLVLSI 2003»
14 years 21 days ago
A practical CAD technique for reducing power/ground noise in DSM circuits
One of the fundamental problems in Deep Sub Micron (DSM) circuits is Simultaneous Switching Noise (SSN), which causes voltage fluctuations in the circuit power/ground networks. In...
Arindam Mukherjee, Krishna Reddy Dusety, Rajsaktis...