279 search results - page 5 / 56 » Efficient Power Co-Estimation Techniques for System-on-Chip ... |
DAC
2005
ACM
13 years 9 months ago
2005
ACM
On-chip supply networks are playing an increasingly important role for modern nanometer-scale designs. However, the ever growing sizes of power grids make the analysis problem ext...
ITC
2003
IEEE
14 years 19 days ago
2003
IEEE
Scan-based architectures, though widely used in modern designs, are expensive in power consumption. In this paper, we present a new technique that allows to design power-optimized...
ASPDAC
2008
ACM
13 years 9 months ago
2008
ACM
- In multi-layered power/ground (P/G) networks, to connect the whole network together, vertical vias are usually placed at intersections between metal wires of adjoining layers. In...
RTSS
1998
IEEE
13 years 11 months ago
1998
IEEE
The energy efficiency of systems-on-a-chip can be much improved if one were to vary the supply voltage dynamically at run time. In this paper we describe the synthesis of systems-...
DAC
2005
ACM
13 years 9 months ago
2005
ACM
Die-to-die and within-die variations impact the frequency and power of fabricated dies, affecting functionality, performance, and revenue. Variation-tolerant circuits and post-sil...