Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint

Scan-based architectures, though widely used in modern designs, are expensive in power consumption. In this paper, we present a new technique that allows to design power-optimized scan chains under a given routing constraint. The proposed technique is a three-phase process based on clustering and reordering of scan cells in the design. It allows to reduce average power consumption during scan testing. Owing to this technique, short scan connections in scan chains are guaranteed and congestion problems in the design are avoided.

• Type: Conference
• Year: 2003
• Where: ITC
• Authors: Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
• Keywords: Hardware, ITC 2003, Power Consumption, Scan, Scan Chains