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HOTDEP
2008
168views Hardware» more  HOTDEP 2008»
13 years 9 months ago
A Spin-Up Saved Is Energy Earned: Achieving Power-Efficient, Erasure-Coded Storage
Storage accounts for a significant amount of a data center's ever increasing power budget. As a consequence, energy consumption has joined performance and reliability as a do...
Kevin M. Greenan, Darrell D. E. Long, Ethan L. Mil...
CASES
2006
ACM
13 years 11 months ago
Power efficient branch prediction through early identification of branch addresses
Ever increasing performance requirements have elevated deeply pipelined architectures to a standard even in the embedded processor domain, requiring the incorporation of dynamic b...
Chengmo Yang, Alex Orailoglu
DFT
2006
IEEE
122views VLSI» more  DFT 2006»
13 years 11 months ago
Efficient and Robust Delay-Insensitive QCA (Quantum-Dot Cellular Automata) Design
The concept of clocking for QCA, referred to as the four-phase clocking, is widely used. However, inherited characteristics of QCA, such as the way to hold state, the way to synch...
Minsu Choi, Myungsu Choi, Zachary D. Patitz, Nohpi...
APCCAS
2006
IEEE
256views Hardware» more  APCCAS 2006»
14 years 1 months ago
Asynchronous Design Methodology for an Efficient Implementation of Low power ALU
— We present a design technique for implementing asynchronous ALUs with CMOS domino logic and delay insensitive dual rail four-phase logic. It ensures economy in silicon area and...
P. Manikandan, B. D. Liu, L. Y. Chiou, G. Sundar, ...
DAC
1996
ACM
13 years 11 months ago
Improving the Efficiency of Power Simulators by Input Vector Compaction
Accurate power estimation is essential for low power digital CMOS circuit design. Power dissipation is input pattern dependent. To obtain an accurate power estimate, a large input...
Chi-Ying Tsui, Radu Marculescu, Diana Marculescu, ...