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ISCA
2006
IEEE
130views Hardware» more  ISCA 2006»
13 years 7 months ago
Area-Performance Trade-offs in Tiled Dataflow Architectures
: Tiled architectures, such as RAW, SmartMemories, TRIPS, and WaveScalar, promise to address several issues facing conventional processors, including complexity, wire-delay, and pe...
Steven Swanson, Andrew Putnam, Martha Mercaldi, Ke...
RTAS
1997
IEEE
13 years 11 months ago
Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
ÐWith effective packet-scheduling mechanisms, modern integrated networks can support the diverse quality-of-service requirements of emerging applications. However, arbitrating bet...
Sung-Whan Moon, Kang G. Shin, Jennifer Rexford
PDCN
2004
13 years 8 months ago
Speculative prefetching of optional locks in distributed systems
We present a family of methods for speeding up distributed locks by exploiting the uneven distribution of both temporal and spatial locality of access behaviour of many applicatio...
Thomas Schöbel-Theuer
BMCBI
2007
106views more  BMCBI 2007»
13 years 7 months ago
Simultaneous identification of long similar substrings in large sets of sequences
Background: Sequence comparison faces new challenges today, with many complete genomes and large libraries of transcripts known. Gene annotation pipelines match these sequences in...
Jürgen Kleffe, Friedrich Möller, Burghar...
BMCBI
2005
162views more  BMCBI 2005»
13 years 7 months ago
Accelerated probabilistic inference of RNA structure evolution
Background: Pairwise stochastic context-free grammars (Pair SCFGs) are powerful tools for evolutionary analysis of RNA, including simultaneous RNA sequence alignment and secondary...
Ian Holmes