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FPL
2005
Springer
131views Hardware» more  FPL 2005»
14 years 28 days ago
An Efficient Approach to Hide the Run-Time Reconfiguration from SW Applications
Dynamically reconfigurable logic is becoming an important design unit in SoC system. A method to make the reconfiguration management transparent to software applications is requir...
Yang Qu, Juha-Pekka Soininen, Jari Nurmi
BMCBI
2008
128views more  BMCBI 2008»
13 years 7 months ago
Efficient computation of absent words in genomic sequences
Background: Analysis of sequence composition is a routine task in genome research. Organisms are characterized by their base composition, dinucleotide relative abundance, codon us...
Julia Herold, Stefan Kurtz, Robert Giegerich
ARC
2008
Springer
115views Hardware» more  ARC 2008»
13 years 9 months ago
A High Throughput FPGA-based Floating Point Conjugate Gradient Implementation
As Field Programmable Gate Arrays (FPGAs) have reached capacities beyond millions of equivalent gates, it becomes possible to accelerate floating-point scientific computing applica...
Antonio Roldao Lopes, George A. Constantinides
DAC
2002
ACM
14 years 8 months ago
A flexible accelerator for layer 7 networking applications
In this paper, we present a flexible accelerator designed for networking applications. The accelerator can be utilized efficiently by a variety of Network Processor designs. Most ...
Gokhan Memik, William H. Mangione-Smith
FPL
2008
Springer
207views Hardware» more  FPL 2008»
13 years 9 months ago
Bitstream compression techniques for Virtex 4 FPGAs
This paper examines the opportunity of using compression for accelerating the (re)configuration of FPGA devices, focusing on the choice of compression algorithms, and their hardwa...
Radu Stefan, Sorin Dan Cotofana