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ERSA
2006
133views Hardware» more  ERSA 2006»
13 years 8 months ago
An FPGA based Co-Design Architecture for MIMO Lattice Decoders
MIMO systems have attracted great attentions because of their huge capacity. The hardware implementation of MIMO decoder becomes a challenging task as the complexity of the MIMO sy...
Cao Liang, Jing Ma, Xin-Ming Huang
JIRS
2007
108views more  JIRS 2007»
13 years 7 months ago
Task-based Hardware Reconfiguration in Mobile Robots Using FPGAs
This paper presents a methodology for the realization of intelligent, task-based reconfiguration of the computational hardware for mobile robot applications. Task requirements are ...
Sesh Commuri, V. Tadigotla, L. Sliger
LCTRTS
2004
Springer
14 years 21 days ago
Asynchronous software thread integration for efficient software
Existing software thread integration (STI) methods provide synchronous thread progress within integrated functions. For the remaining, non-integrated portions of the secondary (or...
Nagendra J. Kumar, Siddhartha Shivshankar, Alexand...
HPCA
2006
IEEE
14 years 7 months ago
An approach for implementing efficient superscalar CISC processors
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...
Shiliang Hu, Ilhyun Kim, Mikko H. Lipasti, James E...
CODES
2009
IEEE
14 years 1 days ago
Native MPSoC co-simulation environment for software performance estimation
Performance estimation of Multi-Processor System-On-Chip (MPa high abstraction level is required in order to perform early architecture exploration and accurate design validations...
Patrice Gerin, Mian Muhammad Hamayun, Fréd&...