19 search results - page 2 / 4 » Efficient Sorting Using Registers and Caches |
17
Voted
ICCD
2002
IEEE
14 years 4 months ago
2002
IEEE
Subword parallelism has succeeded in accelerating many multimedia applications. Subword permutation instructions have been proposed to efficiently rearrange subwords in or among r...
ICS
2007
Tsinghua U.
14 years 1 months ago
2007
Tsinghua U.
The register file is one of the most critical datapath components limiting the number of threads that can be supported on a Simultaneous Multithreading (SMT) processor. To allow t...
CONCURRENCY
2006
13 years 7 months ago
2006
To keep up with a large degree of instruction level parallelism (ILP), the Itanium 2 cache systems use a complex organization scheme: load/store queues, banking and interleaving. ...
IPPS
2010
IEEE
13 years 5 months ago
2010
IEEE
We address the design of algorithms for multicores that are oblivious to machine parameters. We propose HM, a multicore model consisting of a parallel shared-memory machine with hi...
ICDE
2008
IEEE
14 years 9 months ago
2008
IEEE
This paper introduces a framework for processing continuous, exact queries over continuous update XML streams. Instead of eagerly performing the updates on cached portions of the s...