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DAC
2009
ACM
14 years 11 months ago
On systematic illegal state identification for pseudo-functional testing
The discrepancy between integrated circuits' activities in normal functional mode and that in structural test mode has an increasing adverse impact on the effectiveness of ma...
Feng Yuan, Qiang Xu
DFT
2009
IEEE
189views VLSI» more  DFT 2009»
14 years 4 months ago
Analyzing Formal Verification and Testing Efforts of Different Fault Tolerance Mechanisms
Pre-fabrication design verification and post-fabrication chip testing are two important stages in the product realization process. These two stages consume a large part of resourc...
Meng Zhang, Anita Lungu, Daniel J. Sorin
HICSS
2008
IEEE
129views Biometrics» more  HICSS 2008»
14 years 4 months ago
Integration Testing of Composite Applications
A service-oriented architecture enables composite applications that support business processes to be defined and built dynamically from loosely coupled and interoperable web servi...
Liam Peyton, Bernard Stepien, Pierre Seguin
ECBS
2007
IEEE
119views Hardware» more  ECBS 2007»
14 years 4 months ago
IPOG: A General Strategy for T-Way Software Testing
Most existing work on t-way testing has focused on 2-way (or pairwise) testing, which aims to detect faults caused by interactions between any two parameters. However, faults can ...
Yu Lei, Raghu Kacker, D. Richard Kuhn, Vadim Okun,...
ETS
2006
IEEE
110views Hardware» more  ETS 2006»
14 years 4 months ago
Deterministic Logic BIST for Transition Fault Testing
BIST is an attractive approach to detect delay faults due to its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique which was successfully applie...
Valentin Gherman, Hans-Joachim Wunderlich, Jü...