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DATE
1999
IEEE
61views Hardware» more  DATE 1999»
15 years 6 months ago
An Efficient Filter-Based Approach for Combinational Verification
Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayam...
ISCAS
1993
IEEE
133views Hardware» more  ISCAS 1993»
15 years 6 months ago
An efficient FIR filter architecture
– This paper describes an efficient architecture for FIR filters. By exploiting the reduced complexity made possible by the use of sparse powers-of-two coefficients, an FIR ...
Joseph B. Evans
109
Voted
VLSID
1993
IEEE
133views VLSI» more  VLSID 1993»
15 years 6 months ago
An Area-Efficient Systolic Architecture for Real-Time VLSI Finite Impulse Response Filters
An area-eficzent systolic architecture for realtime, programmable-coeBcient jinite impulse response (FIR)filters is presented. A technique called pipelined clustering is introduce...
V. Visvanathan, Nibedita Mohanty, S. Ramanathan
ICPP
1989
IEEE
15 years 6 months ago
Efficient Serial and Parallel Algorithms for Median Filtering
We develop a serial algorithm for separable median filtering that requires only two comparisons per element when the window size is three. In addition, fast parallel CREW PRAM al...
Sanjay Ranka, Sartaj Sahni