An Area-Efficient Systolic Architecture for Real-Time VLSI Finite Impulse Response Filters

An area-eficzent systolic architecture for realtime, programmable-coeBcient jinite impulse response (FIR)filters is presented. A technique called pipelined clustering is introduced t o derive the architecture in which a number of jilter tap computations are multiplexed in an appropriately pipelined processor. This multiplezing is made possible by the fact that the processor is clocked at the highest possible frequency wnder the given. technology and design constraints. Reduction in hardware proportional to the ratio of data arrival period and clock period is ach,ieved. The proposed systolic architecture is 100% eficient and has the sam,e throughput and latency and approximately the same power dissipation as a n unclustered array. The architecture is completely specified, including a description, ofthe m.uHip1exer.sand synchron.isation delays that are required.

• Type: Conference
• Year: 1993
• Where: VLSID
• Authors: V. Visvanathan, Nibedita Mohanty, S. Ramanathan
• Keywords: Area-eficzent Systolic Architecture, Jinite Impulse Response, Systolic Architecture, VLSI, VLSID 1993