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2007
IEEE
14 years 1 months ago
Balancing productivity and performance on the cell broadband engine
— The Cell Broadband Engine (BE) is a heterogeneous multicore processor, combining a general-purpose POWER architecture core with eight independent single-instructionmultiple-dat...
Sadaf R. Alam, Jeremy S. Meredith, Jeffrey S. Vett...
ICC
2007
IEEE
125views Communications» more  ICC 2007»
14 years 1 months ago
A Two-Layer Characteristic-based Rate Control Framework for Low Delay Video Transmission
— In this paper, we present a two-layer rate control In [4], their rate controller TMN8 applied the Lagrange framework for low delay video transmission based on a multiplier to d...
Chun-Yuan Chang, Ming-Hung Chen, Cheng-Fu Chou, Di...
CODES
2006
IEEE
14 years 1 months ago
Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications
The memory subsystem of a complex multiprocessor systemson-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as...
Ilya Issenin, Nikil Dutt
CODES
2005
IEEE
14 years 1 months ago
Memory access optimizations in instruction-set simulators
Design of programmable processors and embedded applications requires instruction-set simulators for early exploration and validation of candidate architectures. Interpretive simul...
Mehrdad Reshadi, Prabhat Mishra
RSP
2000
IEEE
156views Control Systems» more  RSP 2000»
13 years 11 months ago
Quasi-Static Scheduling of Reconfigurable Dataflow Graphs for DSP Systems
Dataflow programming has proven to be popular for representing applications in rapid prototyping tools for digital signal processing (DSP); however, existing dataflow design tools...
Bishnupriya Bhattacharya, Shuvra S. Bhattacharyya