Sciweavers

598 search results - page 68 / 120
» Efficient and User-Friendly Verification
Sort
View
ICCAD
2002
IEEE
146views Hardware» more  ICCAD 2002»
14 years 7 months ago
Conflict driven learning in a quantified Boolean Satisfiability solver
Within the verification community, there has been a recent increase in interest in Quantified Boolean Formula evaluation (QBF) as many interesting sequential circuit verification ...
Lintao Zhang, Sharad Malik
ISMVL
2007
IEEE
104views Hardware» more  ISMVL 2007»
14 years 5 months ago
Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL
Designing modern circuits comprised of millions of gates is a very challenging task. Therefore new directions are investigated for efficient modeling and verification of such syst...
Mahsan Amoui, Daniel Große, Mitchell A. Thor...
GLVLSI
2005
IEEE
97views VLSI» more  GLVLSI 2005»
14 years 4 months ago
On equivalence checking and logic synthesis of circuits with a common specification
In this paper we develop a theory of equivalence checking (EC) and logic synthesis of circuits with a common specification (CS). We show that two combinational circuits N1, N2 have...
Eugene Goldberg
ICISC
2001
162views Cryptology» more  ICISC 2001»
14 years 5 days ago
Content Extraction Signatures
Motivated by emerging needs in online interactions, we define a new type of digital signature called a `Content Extraction Signature' (CES). A CES allows the owner, Bob, of a...
Ron Steinfeld, Laurence Bull, Yuliang Zheng
ESORICS
2009
Springer
14 years 11 months ago
Towards a Theory of Accountability and Audit
Accountability mechanisms, which rely on after-the-fact verification, are an attractive means to enforce authorization policies. In this paper, we describe an operational model of ...
Radha Jagadeesan, Alan Jeffrey, Corin Pitcher, Jam...