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» Efficient and User-Friendly Verification
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126
Voted
DFT
2009
IEEE
189views VLSI» more  DFT 2009»
15 years 10 months ago
Analyzing Formal Verification and Testing Efforts of Different Fault Tolerance Mechanisms
Pre-fabrication design verification and post-fabrication chip testing are two important stages in the product realization process. These two stages consume a large part of resourc...
Meng Zhang, Anita Lungu, Daniel J. Sorin
122
Voted
DAC
2005
ACM
15 years 5 months ago
Smart diagnostics for configurable processor verification
This paper describes a novel technique called Embedded Test-bench Control (ETC), extensively used in the verification of Tensilica’s latest configurable processor. Conventional ...
Sadik Ezer, Scott Johnson
124
Voted
DATE
2008
IEEE
95views Hardware» more  DATE 2008»
15 years 10 months ago
Improving Constant-Coefficient Multiplier Verification by Partial Product Identification
Constant-coefficient multipliers are fundamental components in digital signal processing and arithmetic-based systems. Their verification, however, remains difficult and time-cons...
Chao-Yue Lai, Chung-Yang Huang, Kei-Yong Khoo
133
Voted
RV
2010
Springer
171views Hardware» more  RV 2010»
15 years 1 months ago
Runtime Verification for Software Transactional Memories
Software transactional memories (STMs) promise simple and efficient concurrent programming. Several correctness properties have been proposed for STMs. Based on a bounded conflict ...
Vasu Singh
138
Voted
ICCS
2007
Springer
15 years 10 months ago
Equivalent Semantic Translation from Parallel DEVS Models to Time Automata
Dynamic reconfigurable simulation based on Discrete Event System Specification (DEVS) requires efficient verification of simulation models. Traditional verification method of DEVS ...
Shoupeng Han, Kedi Huang