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» Efficient checker processor design
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DATE
2009
IEEE
139views Hardware» more  DATE 2009»
14 years 2 months ago
Cross-architectural design space exploration tool for reconfigurable processors
—Processors that deploy fine-grained reconfigurable fabrics to implement application-specific accelerators ondemand obtained significant attention within the last decade. They tr...
Lars Bauer, Muhammad Shafique, Jörg Henkel
CSREAESA
2006
13 years 8 months ago
An Efficient Design of High Speed Network Security Platform using Network Processor
: The explosive growth of internet traffic and the increasing complexity of the functions performed by network nodes have given rise to a new breed of programmable micro-processors...
Yong-Sung Jeon, Sang-Woo Lee, Ki-Young Kim
ISPAN
2000
IEEE
13 years 11 months ago
Versatile Processor Design for Efficiency and High Performance
We present new architectural concepts for uniprocessor designs that conform to the data-driven computation paradigm. Usage of our D2 -CPU (Data-Driven processor) follows the natura...
Sotirios G. Ziavras
FPGA
2008
ACM
129views FPGA» more  FPGA 2008»
13 years 9 months ago
Efficient ASIP design for configurable processors with fine-grained resource sharing
Application-Specific Instruction-set Processors (ASIP) can improve execution speed by using custom instructions. Several ASIP design automation flows have been proposed recently. ...
Quang Dinh, Deming Chen, Martin D. F. Wong
CF
2005
ACM
13 years 9 months ago
An efficient wakeup design for energy reduction in high-performance superscalar processors
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
Kuo-Su Hsiao, Chung-Ho Chen