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» Efficient checker processor design
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EUROMICRO
1996
IEEE
13 years 11 months ago
Software Monitoring and Debugging Using Compressed Signature Sequences
Signature based error detection techniques (e.g. the application of watchdog processors) can be easily extended to support software debugging. The run-time sequence of signatures ...
István Majzik
IEEEPACT
2007
IEEE
14 years 1 months ago
Paceline: Improving Single-Thread Performance in Nanoscale CMPs through Core Overclocking
Under current worst-case design practices, manufacturers specify conservative values for processor frequencies in order to guarantee correctness. To recover some of the lost perfo...
Brian Greskamp, Josep Torrellas
FMSD
2006
140views more  FMSD 2006»
13 years 7 months ago
Dealing with practical limitations of distributed timed model checking for timed automata
Two base algorithms are known for reachability verification over timed automata. They are called forward and backwards, and traverse the automata edges using either successors or p...
Víctor A. Braberman, Alfredo Olivero, Ferna...
MICRO
2007
IEEE
150views Hardware» more  MICRO 2007»
14 years 1 months ago
Leveraging 3D Technology for Improved Reliability
Aggressive technology scaling over the years has helped improve processor performance but has caused a reduction in processor reliability. Shrinking transistor sizes and lower sup...
Niti Madan, Rajeev Balasubramonian
DAC
2003
ACM
14 years 8 months ago
Automatic trace analysis for logic of constraints
Verification of system designs continues to be a major challenge today. Simulation remains the primary tool for making sure that implementations perform as they should. We present...
Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Wat...