544 search results - page 8 / 109 » Efficient checker processor design |
FMCAD
1998
Springer
13 years 11 months ago
1998
Springer
We present a new approach to the verification of hardware systems with data dependencies using temporal logic symbolic model checking. As a benchmark we take Tomasulo's algori...
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
Researchers previously proposed warp processors, a novel architecture capable of transparently optimizing an executing application by dynamically re-implementing critical kernels ...
CSE
2009
IEEE
13 years 8 months ago
2009
IEEE
In this paper we present the design of a novel embedded processor architecture (which we call a
CASES
2001
ACM
13 years 11 months ago
2001
ACM
The general purpose processor has long been the focus of intense optimization efforts that have resulted in an impressive doubling of performance every 18 months. However, recent ...
PATMOS
2005
Springer
14 years 27 days ago
2005
Springer
Abstract. The load-store queue (LQ-SQ) of modern superscalar processors is responsible for keeping the order of memory operations. As the performance gap between processing speed a...