555 search results - page 10 / 111 » Efficient event-driven simulation of parallel processor arch... |
ICS
2000
Tsinghua U.
13 years 11 months ago
2000
Tsinghua U.
The rapid advancements of networking technology have boosted potential bandwidth to the point that the cabling is no longer the bottleneck. Rather, the bottlenecks lie at the cros...
HPCC
2007
Springer
13 years 11 months ago
2007
Springer
This paper proposes a highly efficient MBRP parallel algorithm for H.264 encoder, which is based on the analysis of data dependencies in H.264 encoder. In the algorithm, the video ...
IPPS
1998
IEEE
13 years 11 months ago
1998
IEEE
This paper describes a new parallel algorithm for Minimum Cost Path computation on the Polymorphic Processor Array, a massively parallel architecture based on a reconfigurable mesh...
IPPS
2008
IEEE
14 years 1 months ago
2008
IEEE
SIMD (single instruction multiple data)-type processors have been found very efficient in image processing applications, because their repetitive structure is able to exploit the...
ICCAD
2009
IEEE
13 years 5 months ago
2009
IEEE
A parallel computing approach for large-scale SPICE-accurate circuit simulation is described that is based on a new preconditioned iterative solver. The preconditioner involves the...