555 search results - page 14 / 111 » Efficient event-driven simulation of parallel processor arch... |
VLSID
2003
IEEE
2003
IEEE
Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks
14 years 8 months ago
We present an innovative design of an accurate, 2D DCT IDCT processor, which handles scaled and sub-sampled input blocks efficiently. In the IDCT mode, the latency of the processo...
HPCA
2003
IEEE
14 years 8 months ago
2003
IEEE
We study the hardware cost of implementing hash-tree based verification of untrusted external memory by a high performance processor. This verification could enable applications s...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
Computational grids and grid middleware offer unprecedented computational power and storage capacity, and thus, have opened the possibility of solving problems that were previousl...
IPPS
2008
IEEE
14 years 2 months ago
2008
IEEE
Processing nodes of the Cray XT and IBM Blue Gene Massively Parallel Processing (MPP) systems are composed of multiple execution units, sharing memory and network subsystems. Thes...
ISPAN
2000
IEEE
13 years 12 months ago
2000
IEEE
We present new architectural concepts for uniprocessor designs that conform to the data-driven computation paradigm. Usage of our D2 -CPU (Data-Driven processor) follows the natura...